1. Field of the Invention
The present invention relates to a charge pump technology and, more particularly, to a charge pump device capable of eliminating the body effect and having a high pumping gain and an operating method thereof.
2. Description of Related Art
Negative voltages are required for general flash memories or electrically erasable programmable read only memories (EEPROM) to generate a sufficient relative potential difference for data erase or data programming function.
FIG. 1 shows a prior art charge pump device 10, which makes use of cascaded PMOS transistors to transfer charges in the load capacitor of the output node. The input node of this charge pump device 10 is grounded. The drain of each of the PMOS transistors P0˜P4 is connected to the gate thereof. The PMOS transistors are cascaded together in the so-called diode-connected manner. All the substrates of the PMOS transistors P0˜P4 are biased at the voltage level VDD of the power source. The input node and the drain of the transistor P0 are connected to the node D1. The source of the transistor P1 and the drain of the transistor P2 are connected to the node D2. The source of the transistor P2 and the drain of the transistor P3 are connected to the node D3. The source of the transistor P3 and the drain of the transistor P4 are connected to the node D4. The source of the transistor P4 is connected to the output node. The nodes D1˜D4 are connected to capacitors C1˜C4 (all of the same capacitance value of C), respectively.
Please refer to FIGS. 1(a) and 1(b) at the same time. The capacitors C1 and C3 are connected to a first clock signal A, and the capacitors C2 and C4 are connected to a second clock signal B. The first clock signal A and the second clock signals B are mutually opposite in phase, and change their signal levels between the voltage level of the power source and the ground level.
When the voltage level of the first clock signal A is at the voltage level VDD of the power source, the voltage levels of the nodes D1 and D3 are increased by VC=VDD×C/(CP+C) through the coupling of the capacitors C1 and C3, where CP is the parasitic capacitance value of the node D1 or D3. At the same time, the voltage level of the second clock signal B is at the ground level, and the voltage levels of the nodes D2 and D4 are decreased by VC=VDD×C/(CP+C) through the coupling of the capacitors C2 and C4, where CP is the parasitic capacitance value of the node D2 or D4. Because the voltage levels of the nodes D1 and D3 are raised while the voltage levels of the nodes D2 and D4 are lowered, the transistors P0, P2 and P4 are on, and currents flow from the nodes D1 and D3 and the output node to the input node (the ground terminal), and the nodes D2 and D4, respectively. Before the end of the voltage level VDD of the first clock signal A, the voltage levels of the nodes D1 and D3 and the output node will drop because charges in the capacitors C1 and C3 and the load capacitor Cout are transferred to the ground terminal and the capacitors C2 and C4, respectively.
On the contrary, when the voltage level of the first clock signal A is at the ground level, the voltage levels of the nodes D1 and D3 are decreased by VC=VDD×C/(CP+C) through the coupling of the capacitors C1 and C3. At the same time, the voltage level of the second clock signal B is at voltage level VDD of the power source, and the voltage levels of the nodes D2 and D4 are increased by VC=VDD×C/(CP+C) through the coupling of the capacitors C2 and C4. Because the voltage levels of the nodes D1 and D3 are lowered while the voltage levels of the nodes D2 and D4 are raised, the transistors P1 and P3 are on, and currents flow from the nodes D2 and D4 to the nodes D1 and D3, respectively. Before the end of the ground level of the first clock signal A, the voltage levels of the nodes D2 and D4 will drop because charges in the capacitors C2 and C4 and the load capacitor Cout are transferred to the capacitors C1 and C3, respectively. Therefore, through the continual interaction to the capacitors C1˜C4 by the first clock signal A and the second clock signal B, the current constantly flows from the output node to the ground terminal to continually lower the voltage level of the output node, finally reaching the desired negative voltage.
The threshold voltages of the PMOS transistors of the above charge pump device 10 are raised because the potential difference between the substrate and the source (VBS=VDD−VS where VS is a negative voltage) is affected by the reduced voltage level of the source. This is the so-called body effect. An obvious body effect or a raised threshold voltage of a transistor will reduce the conduction performance (charge transfer efficiency) of the transistor. Higher threshold voltages of the PMOS transistors P0˜P4 in FIG. 1(a) means more PMOS transistors are cascaded to cause an inferior charge transfer efficiency so as to be unable to provide an efficient load current. That is, the generated negative voltage is smaller (closer to the ground level, 0V).
FIG. 2(a) shows another prior art charge pump device 20. Reference is made to FIG. 2(b) as well as FIG. 2(a). The charge pump device 20 makes use of NMOS transistors to transfer charges in the load capacitor of the output node. The charge pump device 20 differs from the above charge pump device 10 in that the PMOS transistors P0˜P4 of the charge pump device 10 are replaced with NMOS transistors N0˜N4. The drain of each of the NMOS transistors N0˜N4 is connected to the gate thereof. The NMOS transistors are cascaded together in the so-called diode-connected manner. The principle of operation of FIG. 2(a) is the same as that of FIG. 1(a). Therefore, the charge pump device 20 also has an obvious body effect or raised threshold voltages of transistor, hence lowering the conduction performance (charge transfer efficiency) of transistor. Accordingly, the present invention aims to propose a charge pump device and an operating method thereof in order to solve the above problems in the prior art.